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Surya Veeraraghavan, Austin, Ed Bluestein Blvd
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Anne Marie H Veeraraghavan, Greenlee, Austin, TX ,
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Anne's possible relatives include Joanne Oconnorhynek, Adrienne Hynekmargie, Daniel P Hynek, Surya Veeraraghavan and Shoba Veeraraghavan.
WhitePages: Surya Veeraraghavan | Whitepages
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Daniel Tan at Freescale Semiconductor Contact Details | LeadFerret.com
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Surya Veeraraghavan Distinguished Member Technical Staff · Swati Jain Modeling Engineer · Sylvia Headrick Software Engineer · Todd Davey Global ...
Interests
Surya Veeraraghavan - Patents
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Surya Veeraraghavan patents Recent bibliographic sampling of Surya Veeraraghavan patents listed/published in the public domain by the USPTO (USPTO Patent …
Business Profiles
patentbuddy: Surya Veeraraghavan
FREESCALE SEMICONDUCTOR, INC., Austin, TX, US
Books & Literature
Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs - Jerry G....
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Understand the theory, design and applications of the two principal candidates for the next mainstream semiconductor-industry device with this concise and...
SOI Circuit Design Concepts - Kerry Bernstein, Norman J. Rohrer -...
books.google.de
... Surya Veeraraghavan, Michael Mendicino, Troy Cooper, Skip Egley, and Kevin Cox, "Temperature Dependent Hysteretic Propagation Delay in FB SOI ...
Related Documents
CiteSeerX — On the Gate Capacitance Limits of Nanoscale DG and FD SOI...
citeseerx.ist.psu.edu
@MISC{Ge_onthe, author = {Lixin Ge and Francisco Gámiz and Senior Member and Glenn (chip O. Workman and Surya Veeraraghavan and …
A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk ...
www.nsti.org
Surya Veeraraghavan, Drew Suh, Srinath Krishnan,. Duckhyun Chang, Chip Workman, Keunwoo Kim, Meng. Chiang, Mario Pelella, Li Ge, and Ji-woon Yang.
CiteSeerX — A Compact Model for Valence-Band Electron Tunneling...
citeseerx.ist.psu.edu
... (chip O. Workman and Surya Veeraraghavan and Senior Member and Colin C. Mcandrew and Ronald Van Langevelde and Geert D. J. Smit and Andries J. Scholten …
A surface potential-based compact model of n-MOSFET gate-tunneling...
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... Ten-Lon Chen, Gennady Gildenblat, Senior Member, IEEE, Glenn O. Workman, Member, IEEE, Surya Veeraraghavan, Senior Member, IEEE, ...
Scientific Publications
dblp: Surya Veeraraghavan
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List of computer science publications by Surya Veeraraghavan
dblp: BibTeX records: Surya Veeraraghavan
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List of computer science publications by BibTeX records: Surya Veeraraghavan
Publications
Alternate Structures for Nanoelectronic Applications | SpringerLink
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In this chapter, a review of the alternate MOS structures at the nanoscale has been done. Various potential candidates have been discussed as a replacement to...
Airiti Library華藝線上圖書館
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[1.2]SURYA VEERARAGHAVAN and JERRY.FOSSUM, ”Short-Channel Effects in SOI MOSFET's.”IEEE Trans. Electron Devices, Vol. 36, No 3. pp ,March, 連結：; [1.3]H. Wang, M. Chan, Y. Wang, and P. K. Ko, ”The Behavior of Narrow -Width MOSFET's with MESA Isolation,” IEEE Trans. Electron Devic -es, Vol.
Miscellaneous
Surya Veeraraghavan | LinkedIn
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View Surya Veeraraghavan’s professional profile on LinkedIn. LinkedIn is the world's largest business network, helping professionals like Surya Veeraraghavan ...
US A1 - Method and apparatus for forming a...
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A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a...
Surya Veeraraghavan and Anne Mar | Greenlee Drive, Austin, TX...
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Surya Veeraraghavan and Anne Mar, Greenlee Drive, Austin, TX Find homes for sale, market statistics, foreclosures, property taxes, real estate news,...
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Model selection for SOI MOSFET circuit simulation | Semantic Scholar
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Semantic Scholar extracted view of
US B2 - Method and apparatus for forming an SOI body-contacted...
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Erfinder, Surya Veeraraghavan, Yang Du, Glenn O. Workman. Ursprünglich Bevollmächtigter, Freescale Semiconductor, Inc. Zitat exportieren, BiBTeX, EndNote, ...
US A - Field-effect transistor with perovskite oxide channel...
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1989, Surya Veeraraghavan, et al., Short Channel Effects In SOI MOSFET s , pp , *, IEEE Transactions on Electron Devices, vol.
US B2 - Split level shallow trench isolation for area efficient...
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Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI...
An Open Letter to Congress Concerning H.R.1 - Alana Van Dervort -...
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Melanie Ueland, BA RNC-OB, Spouse has PhD, we could not have afforded the taxes on his fellowship!, University of Minnesota Medical Center Dawn...
Veeraraghavan, US - Patent applications
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Veeraraghavan, US Ashok Veeraraghavan, Cambridge, MA US. Patent application number Description Published; ... Surya Veeraraghavan, Austin, TX US. Patent …
Alumni US | Indian Institute of Technology, Bombay
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Graduates of Indian Institute of Technology, Bombay - the names, photos, skill, job, location. Information on the Indian Institute of Technology, Bombay -...
WO A3 - Method and apparatus for forming a...
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Inventors, Lixin Ge, Leo Mathew, Surya Veeraraghavan. Applicant, Freescale Semiconductor Inc, Lixin Ge, Leo Mathew, Surya Veeraraghavan. Export Citation ...
US B2 - Semiconductor device with increased breakdown voltage...
patents.google.com
US , 12 Dec 2003, 16 Jun 2005, Surya Veeraraghavan, Method and apparatus for forming an SOI body-contacted transistor. US ,
WO A2 - Procede et appareil pour former un transistor de...
patents.google.com
Išradėjai, Surya Veeraraghavan, Yang Du, Glenn O. Workman. Pareiškėjas, Freescale Semiconductor, Inc. Eksportuoti šaltinį, BiBTeX, EndNote, RefMan.
TDGS - "Gennady Gildenblat"
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... , Surya Veeraraghavan, Colin C. McAndrew, Ronald van Langevelde , Geert D. J. Smit, Andries J ...
Benjamin Horn Records Total - People Finder
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Surya Veeraraghavan Deron J Vanhoff Lilia Abeyta Vanhorn Brian Christopher Sullivan Patricia A Vanhorn Kelley Ann Lightfoot Benjamin F Vanhorn Associated names. Benjamin F Vanhorn, Benjamin F Vanhorn, Horn Benjamin Van, Benjamin Frank Vanhorn, B F Vanhorn. Benjamin Franklin Horn.
Defensive publication in Freescale Semiconductors: - PDF
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Bulusu Anand, Shivananda Reddy, Surya Veeraraghavan, A Method to Find Sensitivity of Standard Cells to Process/Model Changes, Defensive Publication of ...
WO A1 - Procédé et appareil à utiliser dans l'amélioration...
patents.google.com
US *, 12 Dec 2003, 16 Jun 2005, Surya Veeraraghavan, Method and apparatus for forming an SOI body-contacted transistor ...
US B2 - Method and structure for SOI body contact FET with...
patents.google.com
In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying...
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