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	Fribourg Lausanne Suisse Switzerland

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Google Groups: crossing clock domain ??

: Matthieu Cattin comp arch fpga Signal can change on each rising edge or less often. "John_H" wrote in ...

Google Groups: FIFO LogiCore with ISE 8.2 ??

: Matthieu Cattin comp arch fpga Hi all, I've created 2 different FIFO with Xilinx Core Generator. I insert the first one in my design ...

Google Groups: P160 analog module ?

: Matthieu Cattin comp arch fpga Hi, I just buy a P160 analog module from Memec Design and I'd like to know the type of the 7 analog ...

Google Groups: Xilinx ISE 8.2 implementation problem

: Matthieu Cattin comp arch fpga Hi, I'm using ISE i and Synplify as synthesis tool. For one of my project, ...

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